By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland collage, Germany. It includes a gate point building of a multi-core computer with pipelined MIPS processor cores and a sequentially constant shared memory.
The ebook includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache dependent sequentially constant shared reminiscence. This opens how to the formal verification of synthesizable for multi-core processors within the future.
Constructions are in a gate point version and therefore deterministic. against this the reference types opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.
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Additional resources for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof
Finally, from the register semantics of the digital model we conclude for t ∈ [e(c + 1) + σ, e(c + 2) + ρ]: x[i](t) = x[i]inc x[i]c x[i]cec = 1 x[i]cec = 0 = x[i]c+1 . This shows part 1 of the lemma for all signals y with d(y) = 0. 6, we get part 1 for all other circuit signals and conclude the proof. 54 3 Hardware Rinn−1 Rin0 Rn−1 ··· R0 Rce Fig. 26. 5). From now on we assume correct timing and stick to the usual digital model unless we need to prove properties not expressible in this model – like the absence of glitches.
Glitches are an issue in the construction of memory systems: accesses to dynamic RAM tend to take several hardware cycles and inputs have to be constant in the digital sense and free of glitches during this time. The latter requirement cannot be expressed in the usual digital model, and thus the lemmas establishing their absence in our construction would be isolated from the remainder of the theory without the detailed model. We explain how timing analysis is performed in the detailed model and then show that, with proper timing analysis, the digital model is an abstraction of the detailed model.
In this case evaluate fi (e1 , . . , eni )(a) by evaluating arguments ej (a), substituting the result into f and evaluating f : fi (e1 , . . , eni )(a) = fi (e1 (a), . . , eni (a)) . The following small example shows that this very formal and detailed set of rules captures our usual way of evaluating expressions: (x1 ∧ x2 )(0, 1) = x1 (0, 1) ∧ x2 (0, 1) = 0∧1 =0. Boolean equations, therefore, are written as e=e , where e and e are expressions involving variables x = x[1 : n]. They come in two ﬂavors: • Identities.
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