By Himanshu Bhatnagar
Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment version describes the complex strategies and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the complete ASIC layout movement technique certain for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time program of Synopsys instruments, used to strive against numerous difficulties noticeable at VDSM geometries. Readers can be uncovered to an efficient layout method for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to format, actual synthesis, and static timing research. At each one step, difficulties relating to each one part of the layout stream are pointed out, with recommendations and work-around defined intimately. furthermore, an important concerns concerning structure, along with clock tree synthesis and back-end integration (links to format) also are mentioned at size. in addition, the ebook includes in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding kinds, exact in the direction of optimum synthesis resolution. objective audiences for this e-book are practising ASIC layout engineers and masters point scholars venture complex VLSI classes on ASIC chip layout and DFT suggestions.
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Extra resources for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
This means that the original netlist that 10 Chapter 1 goes into the layout tool is modified. The formal technique is used to verify the logic equivalency of the modified netlist against the original netlist. 5 Static Timing Analysis using PrimeTime As previously mentioned, the block level static timing analysis is done using DC. Although, the chip-level static timing can be performed using the above approach, it is recommended that PrimeTime, be used instead. PrimeTime is the Synopsys stand-alone sign-off quality static timing analysis tool that is capable of performing extremely fast static timing analysis on full chip-level designs.
Port the netlist and the placement information over to the layout tool. 7. Insert clock tree in the design using the layout tool. 8. Formal verification between clock tree inserted netlist and the original scan inserted netlist. 9. Perform detailed routing using the layout tool. 10. Extract real timing delays from the detailed routed design. 11. Back-annotate the real extracted data to PrimeTime. 12. Post-layout static timing analysis using PrimeTime. 13. Functional gate-level simulation of the design with post-layout timing (if desired).
During this, the same timing constraints that were fed to DC previously are also fed to PrimeTime, specifying the relationship between the primary I/O signals and the clock. If the timing for all critical paths is acceptable, then a constraints file may be written out from PrimeTime or DC for the purpose of forward annotation to the layout tool. This constraint file in SDF format specifies the timing between each group of logic that the layout tool uses, in order to perform the timing driven placement of cells.
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