By Jesper Larsson Träff, Sascha Hunold, Francesco Versaci

This e-book constitutes the refereed court cases of the twenty first overseas convention on Parallel and dispensed Computing, Euro-Par 2015, held in Vienna, Austria, in August 2015. The fifty one revised complete papers offered including 2 invited papers have been conscientiously reviewed and chosen from a hundred ninety submissions. The papers are prepared within the following topical sections: help instruments and environments; functionality modeling, prediction and assessment; scheduling and cargo balancing; structure and compilers; parallel and allotted information administration; grid, cluster and cloud computing; allotted structures and algorithms; parallel and disbursed programming, interfaces and languages; multi- and many-core programming; conception and algorithms for parallel computation; numerical tools and purposes; and accelerator computing.

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In fact, the collaboration between the heterogeneous parallel hardware and the runtime layer seems appropriated to keep the programmability hardship that we are anticipating within acceptable levels while dealing with the Memory, Power and Reliability Walls. However, this is not enough to overcome all the problems that multicores already have to face. To properly take advantage of their potential, tight hardware-software collaboration is required. The runtime has to drive the 18 M. Casas et al.

4x better than the next-best vectorized sorting algorithm when run on the same hardware configuration. 4 Reliability Wall Relying on error detection techniques already available in commodity hardware, we develop algorithmic-level error correction techniques for Detected and Uncorrected Errors (DUE) in iterative solvers. When a data loss or corruption is detected, we use simple algorithmic redundancies that are not applicable under coarser grain error models without paying prohibitive overheads. By using this straightforward relations existing in the solver it is possible to interpolate the lost data and manage to recover it.

VLU also uses a single vector register as input but produces a vector mask as a result that marks the last instance of any particular value found. We provide a suitable hardware proposal that includes both serial and parallel 22 M. Casas et al. variants, demonstrating that the algorithm scales well when increasing the maximum vector length, and works well both with and without parallel lockstepped lanes. VSR sort is a clear example of the benefits that a hardware/software co-designed system can offer.

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