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NRZ timing recovery technique for band limited channels” 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p. 194-5. [46] Van de Plassche, R. Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 1994. T. J. et al. “A 1-Gb/s, four-state, sliding block Viterbi decoder” IEEE Journal of Solid-State Circuits, June 1997. 6, p. 797-805 [49] Spalding, J. et al. 6µm CMOS” 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p.

Electrical Signalling... 29 [42] Poulton, J. et. al. “A Tracking Clock Recovery Receiver for 4Gb/s Signalling”, Hot Interconnects V Symposium Record, August 1997, Stanford, 157-169 [43] Farjad-Rad, R. et al. “An Equalization Scheme for 10Gb/s 4-PAM Signalling over Long Cables” Mixed Signal Conference, July 1997, Cancun, Mexico. , IEEE Press, 1997 [45] Bang-Sup Song et al. “NRZ timing recovery technique for band limited channels” 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p.

Et al. “An Equalization Scheme for 10Gb/s 4-PAM Signalling over Long Cables” Mixed Signal Conference, July 1997, Cancun, Mexico. , IEEE Press, 1997 [45] Bang-Sup Song et al. “NRZ timing recovery technique for band limited channels” 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p. 194-5. [46] Van de Plassche, R. Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 1994. T. J. et al. “A 1-Gb/s, four-state, sliding block Viterbi decoder” IEEE Journal of Solid-State Circuits, June 1997.

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