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CHAPTER THREE SOLUTIONS 30. (a) Define a voltage v across the 1–kΩ resistor with the “+” reference at the top node. Applying KCL at this top node, we find that 80×10–3 – 30×10–3 = v/1000 + v/4000 Solving, v = (50×10–3)(4×106 / 5×103) = 40 V P4kΩ = v2/4000 = 400 mW and (b) Once again, we first define a voltage v across the 1–kΩ resistor with the “+” reference at the top node. Applying KCL at this top node, we find that 80×10–3 – 30×10–3 – 20×10–3 = v/1000 Solving, v = 30 V P20mA = v · 20×10–3 and = 600 mW (c) Once again, we first define a voltage v across the 1–kΩ resistor with the “+” reference at the top node.

Applying KCL and summing the currents flowing out of the top node, v/5,000 + 4×10–3 + 3i1 + v/20,000 = 0 [1] This, unfortunately, is one equation in two unknowns, necessitating the search for a second suitable equation. Returning to the circuit diagram, we observe that i1 or i1 = 3 i1 + v/2,000 = –v/40,000 [2] Upon substituting Eq. [2] into Eq. [1], Eq. 4 µA. Engineering Circuit Analysis, 6th Edition Copyright ©2002 McGraw-Hill, Inc. All Rights Reserved. CHAPTER THREE SOLUTIONS 29. Define a voltage vx with its “+” reference at the center node.

121 Ω-cm. 02714 Ω-cm. Thus, we see that the lower doping level clearly provides material with higher resistivity, requiring less of the available area on the silicon wafer. 121 Ω-cm, we need only define the resistor geometry to complete the design. We typically form contacts primarily on the surface of a silicon wafer, so that the wafer thickness would be part of the factor A; L represents the distance between the contacts. 121 L/(250x10-4 Y) where L and Y are dimensions on the surface of the wafer.

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