By Reis R., Osserian A., Pfleidere H.-J.

This publication includes prolonged and revised models of the simplest papers that have been awarded in the course of the 13th version of the IFIP TC 10 foreign convention on Very huge Scale Integration, an international System-on-Chip layout and CAD convention. the aim of this convention is to supply a discussion board to interchange principles and exhibit commercial and educational study ends up in the sector of microelectronics layout. the present pattern towards expanding chip integration and expertise strategy developments brings approximately stimulating new demanding situations either on the actual and system-design degrees, in addition to within the attempt of those structures.

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8. Electrical signatures when performed DPA attack on bit 4 of the SBOX1. 000 point. As the SBOX1 has four output bits encoded in dual-rail, we have 8 data-paths (from outputs to inputs) which enable to compute 8 values of dxi(tj ). Let’s recall that, dxi(tj )(d0i(tj );d1i(tj )) corresponds to the amount of dissipated power when the attacked bit is processed at time tj . For example, let’s consider the output bit 4 of the SBOX1. Contrary to a standard approach and due to the 8 delay shifts, the values d04(tj ) and d14(tj ) are processed 4 times instead of being processed 32 times, so that their weights are reduced by a factor 8 into sets S1 and S0.

However, for the needs of illustration only the acknowledgment signal of the inputs of the SBOX1 is randomly delayed with 8 different delays. The defined selection function, used to implement the attack, is as follows: D(Cn,P6,K0)= SBOX1(P6⊕ K0) with n ∈ {1,2,3,4} The DPA attack has been implemented on the four output bits of the SBOX1 and on the first iteration of the DES algorithm using 64 plaintext inputs (N=64). Figure 7 shows the current profile of the first iteration when the RTS acknowledgment signal is activated and deactivated.

J. Bainbridge, A. Bardsley, J. D. Garside and S. Temple, “SPA - A Synthesisable Amulet Core for Smartcard Applications”, Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC 2002). Pages 201-210. Manchester, 8-11/04/2002. Published by the IEEE Computer Society. 4. Jacques J. A Fournier, Simon Moore, Huiyun Li, Robert Mullins, and Gerorge Taylor,“Security Evalution of Asunchronous Circuits”, CHES 2003, LNCS 2779, pp 137-151, 2003. 24 F. Bouesse, M. Renaudin, G.

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